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ISL29013
Pin Descriptions
PIN NUMBER
1
2
3
4
PIN NAME
VDD
GND
REXT
INT
DESCRIPTION
Positive supply; connect this pin to a regulated 2.5V to 3.3V supply
Ground pin. The thermal pad is connected to the GND pin
External resistor pin for ADC reference; connect this pin to ground through a (nominal) 100k Ω resistor with
1% tolerance
Interrupt pin; LO for interrupt/alarming. The INT pin is an open drain.
5
6
SCL
SDA
I 2 C serial clock
I 2 C serial data
The I 2 C bus lines can pulled above VDD, 5.5V max.
Principles of Operation
Photodiodes
The ISL29013 contains two photodiode arrays which convert
light into current. One diode is sensitive to both visible and
infrared light, while the other one is only sensitive to infrared
light. Using the infrared portion of the light as baseline, the
visible light can be extracted. The spectral response vs
wavelength is shown in Figure 6 in the “Typical Performance
Curves” on page 11. After light is converted to current during
the light data process, the current output is converted to digital
by a single built-in integrating type signed15-bit Analog-to-
Digital Converter (ADC). An I 2 C command reads the visible
light intensity in counts.
The converter is a charge-balancing integrating type signed
15-bit ADC. The chosen method for conversion is best for
converting small current signals in the presence of an AC
periodic noise. A 100ms integration time, for instance, highly
rejects 50Hz and 60Hz power line noise simultaneously. See
The built-in ADC offers user flexibility in integration time or
conversion time. There are two timing modes: Internal Timing
Mode and External Timing Mode. In Internal Timing Mode,
integration time is determined by an internal dual speed
oscillator (f OSC ), and the n-bit (n = 4, 8, 12,16) counter inside
the ADC. In External Timing Mode, integration time is
determined by the time between two consecutive I 2 C External
Timing Mode commands. See External Timing Mode example.
A good balancing act of integration time and resolution
depending on the application is required for optimal results.
The ADC has four I 2 C programmable range select to
dynamically accommodate various lighting conditions. For
very dim conditions, the ADC can be configured at its lowest
range. For very bright conditions, the ADC can be configured
at its highest range.
3
Interrupt Function
The active low interrupt pin is an open drain pull-down
configuration. The interrupt pin serves as an alarm or
monitoring function to determine whether the ambient light
exceeds the upper threshold or goes below the lower
threshold. The user can also configure the persistency of the
interrupt pin. This eliminates any false triggers such as noise
or sudden spikes in ambient light conditions. An unexpected
camera flash, for example, can be ignored by setting the
persistency to 8 integration cycles.
I 2 C Interface
There are eight (8) 8-bit registers available inside the ISL29013.
The command and control registers define the operation of the
device. The command and control registers do not change until
the registers are overwritten. There are two 8-bit registers that
set the high and low interrupt thresholds. There are four 8-bit
data Read Only registers. Two bytes for the sensor reading and
another two bytes for the timer counts. The data registers
contain the ADC's latest digital output, and the number of clock
cycles in the previous integration period.
The ISL29013’s I 2 C interface slave address is hardwired
internally as 1000100. When 1000100x with x as R or W is
sent after the Start condition, this device compares the first
seven bits of this byte to its address and matches.
Figure 1 shows a sample one-byte read. Figure 2 shows a
sample one-byte write. Figure 3 shows a sync_I 2 C timing
diagram sample for externally controlled integration time.
The I 2 C bus master always drives the SCL (clock) line, while
either the master or the slave can drive the SDA (data) line.
Figure 2 shows a sample write. Every I 2 C transaction begins
with the master asserting a start condition (SDA falling while
SCL remains high). The following byte is driven by the
master, and includes the slave address and read/write bit.
The receiving device is responsible for pulling SDA low
during the acknowledgement period.
Every I 2 C transaction ends with the master asserting a stop
condition (SDA rising while SCL remains high).
For more information about the I 2 C standard, please consult
the Phillips ? I 2 C specification documents.
FN6485.3
November 11, 2011
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